Field of the Invention
This invention relates generally to the design of semiconductor devices and, more particularly, to the identification of parastic transistor structures in the design of a bipolar semiconductor integrated circuit.
Description of the Related Art
For certain voltage conditions, a bipolar integrated circuit chip can include unintended and undesirable transistors that can cause the loss of current during the operation of the circuit. These undesirable transistors are termed parasitic transistors and are created when a high voltage P-diffusion region in an integrated semiconductor device is produced next to a low voltage P-diffusion region or next to a low voltage metal region without the proper isolation between the high voltage and low voltage regions. It is known in the related art of commercially available computer software programs for use as computer-aided tools in the design and analyze solid state integrated circuits. An example of such a software program is the SPICE commercially available circuit analysis program in which nodes of an integrated circuit are user established, parameters defined for the components of the circuit between the nodes, and performance of the circuit computed for a multiciplicity of operating conditions. Circuit analysis programs such as SPICE do not have the capability to graphically display where in the artwork of the integrated circuit a particular node is located for a circuit element. However, the circuit analysis programs can compile a wealth of information about a particular node of a particular circuit element, in particularly, what voltage value results at a particular node for a particular set of input operating parameters. However, this information alone does not help in determining where a parasitic transistor is located.
Similarly, it is known that there is software and computer design tools that can create the corresponding artwork for a particular electrical schematic of an integrated circuit and which will check for land pattern spacing and continuity. However, these software programs and associated design tools, in and of themselves, do not have the capability to perform a circuit analysis on the created artwork to identify what operating condition exists at a particular node for a given set of operating conditions. Again, insufficient information is available to locate a potential parasitic transistor in a semiconductor structure to take corrective action.
Consequently, a need is seen for a method and apparatus which can map an integrated circuit's nodal analysis information, such as the identity of nodes with a designated high voltage value, over to a computer driven software program and associated design tools that can graphically and visually display the location of the nodes and the surrounding artwork containing the particular nodal information, and thus allow for locating parasitic transistors.